1. Field of Invention
This invention relates generally to processors and more specifically to processor architectures.
2. Discussion of Related Art
Processors are well known and widely used in many applications. High end processors are used in supercomputers and other computation intensive applications. Some such processors employ vector architectures. A vector architecture allows the processor to fetch an instruction once and then execute it multiple times with different data. In applications where a significant time is spent in vectorizable loops, the energy required to execute a program can be reduced because, among other factors, each instruction needs to be fetched fewer times per loop. Vector architectures have been generally limited to high end processors because they require significant space on a semiconductor die on which the processor may be implemented.
Even relatively small electronic devices, such as hand held electronic devices, employ processors. Processors used in small electronic devices tend to have a scalar architecture. A processor with a scalar architecture fetches the instruction and data for the instruction each time the instruction is executed. In executing a loop that requires an instruction be executed multiple times, a processor with a scalar architecture will fetch the instruction multiple times. Processors with scalar architectures tend to execute programs more slowly then those with vector architectures. However, they tend to occupy a smaller area on a silicon die, which can be a significant advantage in making a small or low cost processor for an embedded application.
Some scalar processors have been adapted to execute multiple operations for one fetch of an instruction. Such architectures proved difficult in practice to use. The instruction set for the processor needed to be expanded to accommodate many new instructions encoding multiple operations. In addition, making a complier that could identify patterns of instructions in a program that could be mapped to an instruction encoding multiple operations proved difficult.
A related concept is called “software pipelining.” Software pipelining is a technique used in processors that may simultaneously process multiple instructions to implement a “software pipeline,” the order of instructions processed is selected to reduce the total execution time of a block of code.
Some processors employ a “rotating register file.” A rotating register file provides a series of register locations that can be readily accessed by a processor. Successive reads or writes to the same address in the register file can result in accesses to successive locations in the file. When the last location is reached, the succession “rotates” back to the first location. Rotating register files have not heretofore been used in connection with executing vector instructions in the manner described below.
It would be desirable to provide an improved processor architecture.